Recent Advancements in 3D Stacked Memory - Microelectronics TOE

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This issue covers recent advancements in 3D stacked memory technology. Innovations profiled include a vertically stacked memory for high bandwidth by AMD, an architecture to elude channel contention by Carnegie Mellon University, an interconnect test by the Delft University of Technology, and a bidirectional interconnect for 3D stacked memory integration by NVIDIA.

The Microelectronics TechVision Opportunity Engine (TOE) captures global electronics-related innovations and developments on a weekly basis. Developments are centred on electronics attributed by low power and cost, smaller size, better viewing, display and interface facilities, wireless connectivity, higher memory capacity, flexibility and wearables. Research focus themes include small footprint lightweight devices (CNTs, graphene), smart monitoring and control (touch and haptics), energy efficiency (LEDs, OLEDs, power and thermal management, energy harvesting), and high speed and improved conductivity devices (SiC, GaN, GaAs).

Miniaturization, a move toward lower power consumption, and the need for enhanced features are driving innovations in the electronics sector. Technology focus areas include semiconductor manufacturing and design, flexible electronics, 3D integration/IC, MEMS and NEMS, solid state lighting, advanced displays, nanoelectronics, wearable electronics, brain computer interface, advanced displays, near field communication, and next generation data storage or memory.

Keywords: 3D stacked memory, 3D IC

Table of Contents

Recent Advancements in 3D Stacked Memory - Microelectronics TOEInnovations in 3D Stacked MemoryVertically Stacked Memory for High BandwidthArchitecture to Elude Channel Contention in 3D Stacked MemoryInterconnect Test for 3D Stacked Memory Integrated CircuitBidirectional Interconnect for 3D Stacked Memory IntegrationStrategic PerspectivesStrategic PerspectivesStrategic Perspectives (continued) Industry Contacts




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